4-bit counter with the following count sequence (0, 1, 5, 3,7, 9, 11, 13, 15, 14, 12, 10, 2, 4)

module count(cout,clock,reset);

output [3:0]cout;

input clock,reset;

wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17;

wire na,nb,nc,nd;

dff D1(a,da,clock,reset);

dff D2(b,db,clock,reset);

dff D3(c,dc,clock,reset);

dff D4(d,dd,clock,reset);

not n1(na,a);

not n2(nb,b);

not n3(nc,c);

not n4(nd,d);

and a1(w1,nb,a);

and a2(w2,nd,a);

and a3(w3,nc,a);

and a4(w4,nb,nc);

or nexta(da,w1,w2,w3,w4);

and a5(w5,nb,d);

and a6(w6,nb,a,c);

and a7(w7,c,a,d);

and a8(w8,a,b,nc,nd);

and a9(w9,na,b,nc,d);

or nextb(db,w5,w6,w7,w8,w9);

and a10(w10,d,a,c);

and a11(w11,b,d,c);

and a12(w12,b,a,d);

and a13(w13,nc,a,nd);

and a14(w14,b,nc,nd);

or nextc(dc,w10,w11,w12,w13,w14);

and a15(w15,d,c);

and a16(w16,d,a);

and a17(w17,b,c);

or nextd(dd,w15,w16,w17);

buf b1(cout[0],a);

buf b2(cout[1],b);

buf b3(cout[2],c);

buf b4(cout[3],d);

endmodule

TESTBENCH

module count_tb;

wire [3:0]cout;

reg clk,rst;

count CC(cout,clk,rst);

initial

begin

   rst=1'b1;

   #100 rst=1'b0;

  #1800 $finish;

end

always

begin

  clk=1'b1;

  forever #50 clk=~clk;

  end

endmodule

D-flipflop

module dff(q, d, clk, rst);

input d;

input clk, rst;

output reg q;

always @(posedge clk)

begin

if (rst) q <= 0;

else q <= d;

end

endmodule